The present invention relates to a semiconductor device and a related fabrication method. More particularly, the present invention is directed to a semiconductor device having a reduced size suitable for incorporation into a high density integrated circuit on an offset region which is easily controlled.
As shown in FIG. 1, a static random access memory (SRAM) cell can include four N-channel metal oxide semiconductor (NMOS) transistors T3 to T6 and two P-channel metal oxide semiconductor (PMOS) thin film transistors T1 and T2. Generally, the four NMOS transistors T3 to T6 are formed on the semiconductor substrate and the two PMOS transistors T1 and T2 are formed on the NMOS transistors as thin film transistors. Additionally, as further shown in FIG. 1, power supply Vcc is coupled to sources S1 and S2 of transistors T1 and T2, respectively. WL designates a word line and BL and BL represent bit lines for accessing the same cell. Each of transistors T1 to T6 respectively includes sources S1 to S6, gates G1 to G6 and drain electrodes D1 to D6.
A typical SRAM cell having the above-described construction has a relatively large size because the four NMOS and PMOS transistors are laterally disposed near one another on the surface of the substrate. Thus, it is difficult to implement this type of memory cell in a high density memory. Accordingly, in order to fabricate a high-density SRAM cell having densities exceeding 16M, efforts have been made to fabricate smaller transistors.
Accordingly, a conventional transistor having reduced size has been proposed. FIG. 2 shows a cross sectional view of this device.
As shown in FIG. 2, the conventional semiconductor device comprises a substrate 1 and a gate electrode 2 formed thereon. A gate insulating film 3 is provided on the gate electrode 2 and portions of substrate 1 not covered by gate electrode 2. Next, a semiconductor layer including a first impurity region 4a, laterally spaced from gate electrode 2, is provided on gate insulating film 3. The semiconductor layer further includes a second impurity region 4b partially overlapping gate electrode 2 and an offset region 4c formed between the first impurity region 4a and the second impurity region 4b.
A method for fabricating the above-described conventional semiconductor device will now be described with reference to FIGS. 3A-3D.
As shown in FIG. 3A, a metal layer is first deposited on substrate 1 and patterned to form gate electrode 2 using a conventional photolithography process. Next, as shown in FIG. 3B, gate insulating film 3 is deposited on the entire surface of substrate 1 including the gate electrode 2. A polycrystalline active layer 4 and a photosensitive film 5 are then successively deposited on insulating film 3.
As illustrated in FIG. 3C, an offset region is designated by selectively exposing and developing film 5 using an additional offset mask. First and second impurity regions 4a and 4b are formed spaced from one another by implanting a non-volatile ion into the active layer 4 using the patterned photosensitive film 5a as a mask. Lastly, as shown in FIG. 3D, the patterned photosensitive film 5 is selectively removed, leaving portion 4c of active layer 4, covered by film 5a, as an offset region.
An SRAM cell incorporating the above-described conventional semiconductor device will now be described.
FIG. 4 is a cross sectional view illustrating an example of how the conventional semiconductor device described above is incorporated into an SRAM cell. Specifically, FIG. 4 illustrates a bulk transistor and a thin film transistor corresponding to transistors T3 and T2 shown in part A of FIG. 1.
As seen in FIG. 4, a field oxide film 12 is provided to define a field region and an active region on the semiconductor substrate 11. First, gate insulating film 13 is formed on an active region of substrate 11 in isolated relation to the field region, and first gate electrode 14 is formed on the first gate insulating film 13. a sidewall insulating film 16 is formed on both sidewalls of the first gate electrode 14, and first and second impurity regions 17 and 18 are formed in the substrate 11 adjacent respective sidewall insulating films 16.
An interlevel insulating film 21 is formed on the substrate and includes an opening exposing first gate electrode 14. A second gate electrode 22 is formed on the interlevel insulating film 21 and a second gate insulating film 23 is formed on the interlevel insulating film 21 including the second gate electrode 22, except the exposed surface of the first gate electrode 14. Third and fourth impurity regions 24a and 24b are formed spaced from one another on the second gate insulating film 23, and an offset region 24c is formed therebetween. Thus, the bulk transistor includes the first gate insulating film 13, the first gate electrode 14 and the first and second impurity regions 17 and 18, and the thin film transistor includes the third and fourth impurity regions 24a and 24b, the semiconductor region 24c, the second gate insulating film 23, and the second gate electrode 22. The bulk transistor and the thin film transistor are connected electrically by coupling the first gate electrode 14 to the third impurity region 24a.
A method for fabricating the above-described transistor cell will now be described.
A field oxide film 12 is first deposited on substrate 11 defining a field region and an active region using a field oxide process.
Metal is then deposited on a portion of insulating material corresponding to the active region, but not the field region.
The insulating material is then selectively removed using a photolithography and photo-etching process to form the first gate insulating film 13 and the first gate electrode 14. Next, a low concentration impurity ion is implanted on opposite sides of the active region of the semiconductor substrate 11 using the first gate electrode 14 as a mask, thereby forming low concentration impurity concentration LDD regions.
An insulating material is then deposited on the entire semiconductor substrate 11 including the first gate electrode 14, followed by selective removal of the insulating material so that sidewall portions 16 remain on the sides of the first gate electrode 14 and the first gate insulating film 13. Thereafter, high concentration impurity ions (n.sup.+) are implanted into the active region of the semiconductor substrate 11 using sidewalls 16 and the first gate electrode 14 as a mask. As a result, the first and second impurity regions 17 and 18 are formed in connection with the low concentration impurity region 15. The first impurity region 17 is used as a source region of the bulk transistor, and the second impurity region 18 is used as a drain region. An insulating material is deposited over the entire substrate surface to form the interlevel insulating film 21. Portions of interlevel insulating film 21 are then selectively removed using a conventional photolithography process to form a contact hole to expose the first gate electrode 14. A metal layer is then deposited on the entire surface of the interlevel insulating film 21 including the contact hole, and the metal is selectively removed using photolithography to form the second gate electrode 22.
The second gate insulating film 23 is then formed by depositing insulating material on the interlevel insulating film 21 including the second gate electrode 22. Next, polycrystalline silicon is deposited on the interlevel insulating film 21 including the exposed surface of the first gate electrode 14 and the second gate insulating film 23 to form the active film 24. A photosensitive film is then coated onto the substrate and patterned by an exposure and development process using an additional offset mask as illustrated in FIG. 3C to define the offset region on the active film 24. Impurity ions are then implanted into the active film 24 using the patterned photosensitive film as a mask. As a result, third and fourth impurity regions 24a and 24b are formed spaced from one another by offset region 24c. The sensitive film remaining on the offset region is then removed.
However, the conventional semiconductor device employed in an SRAM cell has problems. First, additional masks are needed to form the offset region and the gate electrode of the transistor. Accordingly, the number of fabrication steps is increased, and the overall process becomes complicated. Second, it is hard to accurately align the offset region and the gate electrode from device to device. Therefore, the offset region and the gate electrode become less uniform. Third, by forming the impurity regions laterally spaced from one another, the size of the transistor on the substrate is increased. That is, in the SRAM cell of the conventional semiconductor device, when the thin film transistor is deposited on the bulk transistor, the size of the transistor unit is increased, and it is not suitable for use in a high density memory circuit.